CDC: Xilinx ug953 details domain crossing methods.
Timing closure: Xilinx ug906. ug906-vivado-design-analysis.pdf
Reset fanout: The way to make the tool use the higher fanout trees is to “promote to clock buffer” as they called it for Xilinx. So promote the reset net to clock using a constraint so that it uses clock buffer. Alternatively, instantiate a clock buffer manually in the RTL and route the reset through.
MAX_FAN_OUT constraint applied on the signal reduces the fanout to aid timing closure.
1) Demystifying Resets: Synchronous, Asynchronous other Design Considerations… Part 1
https://forums.xilinx.com/t5/Adaptable-Advantage-Blog/Demystifying-Resets-Synchronous-Asynchronous-other-Design/ba-p/882252
2) Demystifying Resets: Synchronous, Asynchronous other Design Considerations… Part 2
https://forums.xilinx.com/t5/Adaptable-Advantage-Blog/Demystifying-Resets-Synchronous-Asynchronous-and-other-Design/ba-p/887366