Previous to VHDL 2008 use: tcl script: force -deposit value /signal For VDHL 2008 use, new language additions. I like to do this using an alias to the DUT signal and to allow the design team to update their code have an alias to the top level then the testbench alias their top level alias. …
Continue reading Forcing signals
ModelSim -elab
-elab will save an elaborated database for fast reload. Use vsim -loadelab
Stop ModelSim opening files.
set PrefSource(OpenOnBreak) 0
File checksum
Reference: MS certutil doc
C:> certutil -hashfile path-to-your-file SHA256
FlexLm licence info
How to find flexlm license users.
ModelSim environment variables
license env variable: MGLS_LICENSE_FILE=port@ip
Resets and synchronisers
Links to Xilinx CDC and timing closure documentation.
Vivado TCL scripting
See user guides ug835-vivado-tcl-commands.pdf and ug894-vivado-tcl-scripting.pdf
Vivado batch mode
When invoking Vivado tools from DOS, you first need to run the file settings64.bat (located in your Xilinx install area e.g. C:\Xilinx\Vivado\2017.3) in order to get your path updated as appropriate. https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_3/ug975-vivado-quick-reference.pdf
FSM attributes
“fsm_safe_state” attribute will direct Vivado Synthesis to insert logic into a state machine that specifies what should happen in the case of an illegal state. “power_on_state” attribute forces the state machine into the power-on state using Hamming-2 encoding detection for one bit/flip. Reference: 1) https://www.xilinx.com/support/answers/60799.html 2) UG901 v2017.4, Chapter 2 Synthesis Attributes, Page 47, https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug901-vivado-synthesis.pdf