Forcing signals

Previous to VHDL 2008 use:

tcl script: force -deposit value /signal

For VDHL 2008 use, new language additions. I like to do this using an alias to the DUT signal and to allow the design team to update their code have an alias to the top level then the testbench alias their top level alias.

alias dut_probe_my_sig is << signal .tb.dut.alias_dut_sig : unsigned >>
dut_probe_my_sig <= force value;
wait for clock;
dut_probe_my_sig <= release;

Note that there has to be sufficient time allowed for the force to propagate because when the release occurs the signal will return to its original value.

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