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Forcing signals

Posted on July 16, 2021Updated on January 6, 2022by adminCategories:VHDL

Previous to VHDL 2008 use: tcl script: force -deposit value /signal For VDHL 2008 use, new language additions. I like to do this using an alias to the DUT signal and to allow the design team to update their code have an alias to the top level then the testbench alias their top level alias. …
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ModelSim -elab

Posted on July 14, 2021Updated on July 14, 2021by adminCategories:ModelSim, Tools

-elab will save an elaborated database for fast reload. Use vsim -loadelab

Stop ModelSim opening files.

Posted on May 11, 2020Updated on May 11, 2020by adminCategories:ModelSim, TCL scripting

set PrefSource(OpenOnBreak) 0